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1 lt1424-9 sn14249 14249fs isolated flyback switching regulator with 9v output n no transformer third winding or optoisolator required n application circuit meets pcmcia type ii height requirement n fixed, application specific 9v output voltage n regulation maintained well into discontinuous mode (light load) n load compensation provides excellent load regulation n available in 8-pin pdip and so packages n operating frequency: 285khz the lt ? 1424-9 is a monolithic high power switching regulator specifically designed for the isolated flyback topology. no third winding or optoisolator is required; the integrated circuit senses the isolated output voltage directly from the primary side flyback waveform. a high current, high efficiency switch is included on the die along with all oscillator, control and protection circuitry. the lt1424-9 operates with input supply voltages from 3v to 20v and draws only 7ma quiescent current. it can deliver up to 200ma at 9v with no external power devices. by utilizing current mode switching techniques, it pro- vides excellent ac and dc line regulation. the lt1424-9 has a number of features not found on other switching regulator ics. its unique control circuitry can maintain regulation well into discontinuous mode. load compensation circuitry allows for improved load regula- tion. an externally activated shutdown mode reduces total supply current to 20 m a typical for standby operation. C 9v pcmcia type ii isolated lan supply (2.41mm maximum component height) , ltc and lt are registered trademarks of linear technology corporation. n ethernet isolated 5v to C 9v converter features descriptio u applicatio s u typical applicatio u 1424 ta01 2 1 3 4 8 7 6 5 v c shdn sync sgnd r1 75 w r2 75 w 1 2 3 mbrs130lt3 t1 1:1 4 0.1 m f lt1424-9 47pf c5 220pf c6 220pf c3 10 m f 25v c4 10 m f 25v 1.8k out com ?v 200ma 1000pf c1 10 m f 25v 5v input com c2 10 m f 25v 0.1 m f 100k r ccomp v in v sw pgnd c1, c2, c3, c4: marcon thcs50e1e106z ceramic capacitor, size 1812. (847) 696-2000 t1: coiltronics ctx02-13483 isolation barrier d1 1n5248 d2 mbr0540t4
2 lt1424-9 sn14249 14249fs (note 1) supply voltage ........................................................ 20v switch voltage ......................................................... 35v shdn, sync pin voltage ........................................... 7v operating junction temperature range commercial .......................................... 0 c to 125 c industrial ......................................... C 40 c to 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute m axi m u m ratings w ww u package/order i n for m atio n w u u electrical characteristics consult factory for military grade parts. order part number lt1424cn8-9 lt1424cs8-9 lt1424in8-9 lt1424is8-9 s8 part marking 14249 1424i9 t jmax = 145 c, q ja = 130 c/ w (n) t jmax = 145 c, q ja = 110 c/ w (s) 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so n8 package 8-lead pdip shdn v c sync sgnd r ccomp v in v sw pgnd the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 5v, v sw open, v c = 1.4v, unless otherwise specified. symbol parameter conditions min typ max units power supply v in(min) minimum input voltage l 2.8 3.1 v i cc supply current l 7.0 9.5 ma shutdown mode supply current l 15 40 m a shutdown mode threshold l 0.3 0.9 1.3 v feedback amplifier v ref reference voltage measured at v sw pin (note 2) 9.00 9.15 9.30 v l 8.90 9.15 9.40 v g m feedback amplifier transconductance d i c = 10 m a (note 2) l 400 1000 1600 m mho i source , i sink feedback amplifier source or sink current l 30 50 80 m a v cl feedback amplifier clamp voltage 1.9 v reference voltage/current line regulation 5v v in 18v l 0.01 0.04 %/v voltage gain (note 3) 500 v/v output switch bv output switch breakdown voltage i c = 5ma l 35 50 v v(v sw ) output switch on voltage i sw = 1a l 0.55 0.85 v i lim switch current limit duty cycle = 50%, 0 c t j 125 c l 1.35 1.6 1.95 a duty cycle = 50%, C 40 c t j 125 c l 1.20 1.6 1.95 a duty cycle = 80% 1.3 a current amplifier control pin threshold duty cycle = minimum 0.95 1.2 1.3 v l 0.85 1.2 1.4 v control voltage to switch transconductance 2 a/v
3 lt1424-9 sn14249 14249fs note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: v ref is a parameter which is measured at the v sw pin. it differs from the output voltage because it accounts for output diode drop, transformer leakage inductance, etc. nominal output voltage is 9v in the intended application circuit. note 3: feedback amplifier transconductance is r ref referred. note 4: voltage gain is r ref referred. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 5v, v sw open, v c = 1.4v, unless otherwise specified. symbol parameter conditions min typ max units timing f switching frequency 260 285 300 khz l 240 285 320 khz t on minimum switch on time 170 200 260 ns t ed flyback enable delay time 150 ns t en minimum flyback enable time 180 ns maximum switch duty cycle l 85 90 % load compensation d v ref / d i sw 1.5 w sync function minimum sync amplitude l 1.5 2.2 v synchronization range l 330 450 khz sync pin input resistance 40 k w
4 lt1424-9 sn14249 14249fs typical perfor a ce characteristics uw v c pin threshold and high clamp voltage vs temperature reference voltage vs temperature feedback amplifier output current vs flyback voltage shdn pin input current vs voltage switching frequency vs temperature minimum synchronization voltage vs temperature temperature ( c) ?0 reference voltage (v) 9.20 9.25 9.30 25 75 1424-9 g04 9.15 9.10 ?5 0 50 100 125 9.05 9.00 flyback voltage (v) 7.5 60 40 20 0 ?0 ?0 ?0 ?0 9.0 10.0 1424-9 g05 8.0 8.5 9.5 10.5 11.0 feedback amplifier output current ( a) 25 c 125 c ?5 c temperature ( c) ?0 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 25 75 1424-9 g06 ?5 0 50 100 125 v c pin voltage (v) v c high clamp v c threshold temperature ( c) ?0 285 290 300 25 75 1424-9 g07 280 275 ?5 0 50 100 125 270 265 295 switching frequency (khz) temperature ( c) ?0 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 25 75 1424-9 g08 ?5 0 50 100 125 minimum synchronization voltage (v p-p ) shdn pin voltage (v) 0 1 0 ? ? ? ? 4 1424-9 g09 1 2 3 5 shdn pin input current ( a) t a = 25 c switch current (a) 0 switch saturation voltage (v) 1.2 1.0 0.8 0.6 0.4 0.2 0 0.6 1.0 1424-9 g01 0.2 0.4 0.8 1.2 1.4 125 c 25 c ?5 c switch saturation voltage vs switch current minimum input voltage vs temperature switch current limit vs duty cycle duty cycle (%) 0 switch current limit (a) 40 1424-9 g02 10 20 30 50 60 70 80 90 100 2.0 1.5 1.0 0.5 0 t a = 25 c temperature ( c) ?0 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 25 75 1424-9 g03 ?5 0 50 100 125 input voltage (v)
5 lt1424-9 sn14249 14249fs pgnd (pin 5): power ground. this pin is the emitter of the power switch device and has large currents flowing through it. it should be connected directly to a good quality ground plane. v sw (pin 6): this is the collector node of the output switch and has large currents flowing through it. keep the traces to the switching components as short as possible to minimize electromagnetic radiation and voltage spikes. v in (pin 7): supply voltage. bypass input supply pin with 10 m f or more. the part goes into undervoltage lockout when v in drops below 2.8v. undervoltage lockout stops switching and pulls the v c pin low. r ccomp (pin 8): pin for the external filter capacitor for load compensation function. a common 0.1 m f ceramic capacitor will suffice. pi n fu n ctio n s uuu shdn (pin 1): shutdown. this pin is used to turn off the regulator and reduce v in input current to a few tens of microamperes. the shdn pin can be left floating when unused. v c (pin 2): control voltage. this pin is the output of the feedback amplifier and the input of the current compara- tor. frequency compensation of the overall loop is effected by placing a capacitor between this node and ground. sync (pin 3): pin to synchronize internal oscillator to external frequency reference. it is directly logic compat- ible and can be driven with any signal between 10% and 90% duty cycle. if unused, this pin should be tied to ground. sgnd (pin 4): signal ground. this pin is a clean ground. the internal reference and feedback amplifier are referred to it. keep the ground path connection to the v c compen- sation capacitor free of large ground currents. minimum flyback enable time vs temperature minimum switch on time vs temperature flyback enable delay time vs temperature temperature ( c) ?0 200 225 275 25 75 1424-9 g10 175 150 ?5 0 50 100 125 125 100 250 switch on time (ns) temperature ( c) ?0 200 225 250 25 75 1424-9 g11 175 150 ?5 0 50 100 125 125 100 75 enable delay time (ns) temperature ( c) ?0 200 225 275 25 75 1424-9 g12 175 150 ?5 0 50 100 125 125 100 250 enable time (ns) typical perfor a ce characteristics uw
6 lt1424-9 sn14249 14249fs flyback error a plifier diagra ww + d1 t1 isolated v out c1 + v in v sw v c c ext r fb r ref v bg q4 d2 q1 q2 q3 v in i i m i m i fxd enable 1424 ea block diagra m w + load compensation current amplifier driver logic 285khz oscillator 2.6v regulator shdn flyback error amplifier comp r ccomp v sw r sense pgnd 1424bd v c sgnd gnd is omitted for clarity v in sync
7 lt1424-9 sn14249 14249fs ti i g diagra w w u v sw voltage v in gnd off on minimum t on enable delay minimum enable time 1424 td off on switch state flyback amp state 0.80 v flbk v flbk collapse detect enabled disabled disabled
8 lt1424-9 sn14249 14249fs operatio n u the lt1424-9 is a current mode switching regulator ic that has been designed specifically for the isolated fly- back topology. the special problem normally encoun- tered in such circuits is that information relating to the output voltage on the isolated secondary side of the transformer must be communicated to the primary side in order to maintain regulation. historically, this has been done with optoisolators or extra transformer windings. optoisolator circuits waste output power and the extra components they require increase the cost and physical volume of the power supply. optoisolators can also exhibit trouble due to limited dynamic response (tempo- ral), nonlinearity, unit-to-unit variation and aging over life. circuits employing extra transformer windings also exhibit deficiencies. the extra winding adds to the transformers physical size and cost. dynamic response is often mediocre. there is usually no method for main- taining load regulation versus load. the lt1424-9 derives its information about the isolated output voltage by examining the primary side flyback pulse waveform. in this manner no optoisolator nor extra transformer winding is required. this ic is a quantum improvement over previous approaches because: target output voltage is directly resistor programmable, regula- tion is maintained well into discontinuous mode and optional load compensation is available. the block diagram shows an overall view of the system. many of the blocks are similar to those found in tradi- tional designs including: internal bias regulator, oscilla- tor, logic, current amplifier and comparator, driver and output switch. the novel sections include a special flyback error amplifier and a load compensation mecha- nism. also, due to the special dynamic requirements of flyback control, the logic system contains additional functionality not found in conventional designs. the r ref , r rfb and r ocomp resistors in the block diagram are application-specific thin-film resistors internal to the lt1424-9. the capacitor connected to the r ccomp pin is external. the lt1424-9 operates much the same as traditional current mode switchers, the major difference being a different type of error amplifier which derives its feedback information from the flyback pulse. due to space con- straints, this discussion will not reiterate the basics of current mode switcher/controllers and isolated flyback converters. a good source of information on these topics is ltcs application note 19. error amplifierpseudo dc theory please refer to the simplified diagram of the flyback error amplifier. operation is as follows: when output switch q4 turns off, its collector voltage rises above the v in rail. the amplitude of this flyback pulse, i.e., the difference between it and v in , is given as: v flbk = v f = d1 forward voltage i sec = transformer secondary current esr = total impedance of secondary circuit n sp = transformer effective secondary-to-primary turns ratio v out + v f + (i sec )(esr) n sp the flyback voltage is then converted to a current by the action of r fb and q1. nearly all of this current flows through resistor r ref to form a ground-referred voltage. this is then compared to the internal bandgap reference by the differential transistor pair q2/q3. the collector current from q2 is mirrored around and subtracted from fixed current source i fxd at the v c pin. an external capacitor integrates this net current to provide the control voltage to set the current mode trip point. the relatively high gain in the overall loop will then cause the voltage at the r ref resistor to be nearly equal to the bandgap reference v bg . the relationship between v flbk and v bg may then be expressed as: v flbk r fb v flbk = v bg a = ratio of q1 i c to i e v bg = internal bandgap reference a = or, r fb r ref v bg r ref ) ) 1 a ) )
9 lt1424-9 sn14249 14249fs operatio n u combination with the previous v flbk expression yields an expression for v out , in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop: v out = v bg ?v f ?i sec (esr) r fb r ref ) ) n sp a ) ) additionally, it includes the effect of nonzero secondary output impedance. see load compensation for details. the practical aspects of applying this equation for v out are found in the applications information section. so far, this has been a pseudo-dc treatment of flyback error amplifier operation. but the flyback signal is a pulse, not a dc level. provision must be made to enable the flyback amplifier only when the flyback pulse is present. this is accomplished by the dashed line connections to the block labeled enable. timing signals are then required to enable and disable the flyback amplifier. error amplifierdynamic theory there are several timing signals that are required for proper lt1424-9 operation. please refer to the timing diagram. minimum output switch on time the lt1424-9 effects output voltage regulation via flyback pulse action. if the output switch is not turned on at all, there will be no flyback pulse, and output voltage informa- tion is no longer available. this would cause irregular loop response and start-up/latchup problems. the solution chosen is to require the output switch to be on for an absolute minimum time per each oscillator cycle. this in turn establishes a minimum load requirement to maintain regulation. see applications information section for fur- ther details. enable delay when the output switch shuts off, the flyback pulse appears. however, it takes a finite time until the trans- former primary side voltage waveform approximately rep- resents the output voltage. this is partly due to rise time on the v sw node, but more importantly due to transformer leakage inductance. the latter causes a voltage spike on the primary side not directly related to output voltage. (some time is also required for internal settling of the feedback amplifier circuitry.) in order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. this is termed enable delay. in certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. see applications information section for further details. collapse detect once the feedback amplifier is enabled, some mechanism is then required to disable it. this is accomplished by a collapse detect comparator, that compares the flyback voltage (r ref referred) to a fixed reference, nominally 80% of v bg . when the flyback waveform drops below this level, the feedback amplifier is disabled. this action accommodates both continuous and discontinuous mode operation. minimum enable time the feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed minimum enable time. this prevents lock-up, especially when the output voltage is abnormally low, e.g., during start-up. the mini- mum enable time period ensures that the v c node is able to pump up and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. the minimum enable time often determines the low load level at which output voltage regulation is lost. see applications information section for details. effects of variable enable period it should now be clear that the flyback amplifier is enabled only during a portion of the cycle time. this can vary from the fixed minimum enable time described to a maximum of roughly the off switch time minus the enable delay
10 lt1424-9 sn14249 14249fs time. certain parameters of flyback amp behavior will then be directly affected by the variable enable period. these include effective transconductance and v c node slew rate. load compensation theory the lt1424-9 uses the flyback pulse to obtain information about the isolated output voltage. a potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, transformer secondary and output capacitor. this has been represented previously by the expression (i sec )(esr). however, it is generally more useful to convert this expres- sion to an effective output impedance. because the sec- ondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the off duty cycle. that is, r out = esr r out = effective supply output impedance esr = lumped secondary impedance dc off = off duty cycle where, 1 dc off ) ) expressing this in terms of the on duty cycle, remember- ing dc off = 1 C dc, r out = esr dc = on duty cycle 1 1 ?dc ) ) in less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external r fb resistor value adjusted to compensate for nominal expected error. in more demanding applications, output impedance error may be minimized by the use of the load compensation function. to implement the load compensation function, a voltage is developed that is proportional to average output switch current. this voltage is then impressed across the external r ocomp resistor and the resulting current is then sub- operatio n u tracted from the r fb node. as output loading increases, average switch current increases to maintain rough output voltage regulation. this causes an increase in r ocomp resistor current subtracted from the r fb node, through which feedback loop action causes a corresponding increase in target output voltage. assuming a relatively fixed power supply efficiency, eff power out = (eff)(power in) (v out )(i out ) = (eff)(v in )(i in ) average primary side current may be expressed in terms of output current as follows: i in = i out v out (v in )(eff) ) ) combining the efficiency and voltage terms in a single variable, k1 = i in = k1(i out ) where, v out (v in )(eff) ) ) switch current is converted to voltage by a sense resistor and amplified by the current sense amplifier with associ- ated gain g. this voltage is then impressed across the external r ocomp resistor to form a current that is subtracted from the r fb node. so the effective change in v out target is: d v out = k1( d i out ) r fb (r sense )(g) r ocomp ) ) expressing the product of r sense and g as the data sheet value of d v rccomp / d i sw , d v rccomp d i sw ) ) r fb r ocomp ) ) r out = k1 and, d v rccomp d i sw ) ) r fb r out ) ) r ocomp = k1 where, k1 = dimensionless variable related to v in , v out and efficiency as above
11 lt1424-9 sn14249 14249fs operatio n u d v rccomp d i sw d v out d i out ) ) r fb r ocomp ) ) = k1 nominal output impedance cancellation is obtained by equating this expression with r out . d v rccomp d i sw ) ) = data sheet value for r ccomp pin action vs switch current r fb = external feedback resistor value r out = uncompensated output impedance applicatio n s i n for m atio n wu u u the lt1424-x is an application-specific 8-pin part which implements an isolated flyback switcher/controller. three on-chip thin-film resistors are used to program the part for a specific application including mainly desired output voltage, transformer turns ratio and secondary circuit esr behavior. as of initial release, the lt1424-9 is available which implements the C 9v pcmcia ii isolated lan supply as described in the typical application section. potential users with a high volume requirement for other applications are advised as follows: general experimenta- tion/breadboarding may be done with the lt1425. this is a general purpose 16-pin part whose functionality is similar to the lt1424-x, with the exception that the three application resistors are external user-supplied compo- nents. application information relating to the proper selection of these resistor values is contained within the lt1425 data sheet. once technical feasibility is demon- strated, the potential user may discuss the possibility of an additional lt1424-x version with the factory. output voltage error sources conventional nonisolated switching power supply ics typically have only two substantial sources of output voltage error the internal or external resistor divider network that connects to v out and the internal ic refer- ence. the lt1424-9, which senses the output voltage in both a dynamic and an isolated manner, exhibits addi- tional potential error sources to contend with. some of these errors are proportional to output voltage, others are fixed in an absolute millivolt sense. here is a list of possible error sources and their effective contribution: internal voltage reference the internal bandgap voltage reference is, of course, imperfect. its error, both at 25 c and over temperature is already included in the specifications for reference voltage. schottky diode drop the lt1424-9 senses the output voltage from the trans- former primary side during the flyback portion of the cycle. this sensed voltage therefore includes the forward drop, v f , of the rectifier (usually a schottky diode). lot-to-lot and ambient temperature variations will show up as output voltage shift/drift. secondary leakage inductance leakage inductance on the transformer secondary reduces the effective primary-to-secondary turns ratio (n p /n s ) from its ideal value. this increases the output voltage target by a similar percentage and has been nominally taken into account in the design of the lt1424-9. to the extent that secondary leakage induc- tance varies from part-to-part, the output voltage will be affected. output impedance error the lt1424-9 contains a load compensation function to provide a nominal, first-order cancellation of the effects of secondary circuit esr. unit-to-unit variation plus some inherent nonlinearity in the cancellation results in some residual v out variation with load.
12 lt1424-9 sn14249 14249fs applicatio n s i n for m atio n wu u u minimum load considerations the lt1424-9 generally provides better low load perfor- mance than previous generation switcher/controllers utilizing indirect output voltage sensing techniques. spe- cifically, it contains circuitry to detect flyback pulse collapse, thereby supporting operation well into dis- continuous mode. in general, there are two possible constraints to ultimate low load operation, minimum switch on time which sets a minimum level of delivered power, and minimum flyback enable time, which deals with the ability of the feedback system to derive valid output voltage information from the flyback pulse. in the application for which the lt1424-9 is designed, the minimum flyback enable time is more restrictive. the lt1424-9 derives its output voltage information from the flyback pulse. if the internal minimum enable time pulse extends beyond the flyback pulse, loss of regulation will occur. the onset of this condition can be determined by setting the width of the flyback pulse equal to the sum of the flyback enable delay, t ed , plus the minimum enable time, t en . minimum power delivered to the load is then: 1 2 ) ) f l sec ) ) min power = [v out ?(t en + t ed )] 2 = (v out )(i out ) which yields a minimum output constraint: 1 2 ) ) f(v out ) l sec ) ) i out(min) = f = switching frequency (nominally 285khz) l sec = transformer secondary side inductance v out = output voltage t ed = enable delay time t en = minimum enable time (t ed + t en ) 2 , where in reality, the previously derived expression is a conserva- tive one, as it assumes perfectly square waveforms, which is not the case at light load. furthermore, the equation was set up to yield just the onset of control error. in other words, while the equation suggests a minimum load current of perhaps 7ma, laboratory observations suggest operation down to 2ma to 3ma before significant output voltage rise is observed. nevertheless, this situa- tion is addressed in the application by the use of a fixed 1.8k load resistor, which preloads the supply with a nominal 5ma. maximum load/short-circuit considerations the lt1424-9 is a current mode controller. it uses the v c node voltage as an input to a current comparator which turns off the output switch on a cycle-by-cycle basis as this peak current is reached. the internal clamp on the v c node, nominally 1.9v, then acts as an output switch peak current limit. this action becomes the switch current limit specification. the maximum available output power is then determined by the switch current limit, which is somewhat duty cycle dependent due to internal slope compensation action. short-circuit conditions are handled by the same mecha- nism. the output switch turns on, peak current is quickly reached and the switch is turned off. because the output switch is only on for a small fraction of the available period, internal power dissipation is controlled. (the lt1424-9 contains an internal overtemperature shutdown circuit, that disables switch action, just in case.) thermal considerations care should be taken to ensure that the worst-case input voltage and load current conditions do not cause exces- sive die temperatures. the packages are rated at 110 c/w for so-8 and 130 c/w for n8. average supply current (including driver current) is: i sw 35 ) ) i in = 7ma + dc where, i sw = switch current dc = on switch duty cycle switch power dissipation is given by: p sw = (i sw ) 2 (r sw )(dc) r sw = output switch on resistance
13 lt1424-9 sn14249 14249fs applicatio n s i n for m atio n wu u u total power dissipation of the die is the sum of supply current times supply voltage plus switch power: p d(total) = (i in ? v in ) + p sw frequency compensation loop frequency compensation is performed by connect- ing a capacitor from the output of the error amplifier (v c pin) to ground. an additional series resistor, often required in traditional current mode switcher controllers is usually not required; and can even prove detrimental. the phase margin improvement traditionally offered by this extra resistor will usually be already accomplished by the nonzero secondary circuit impedance, which adds a zero to the loop response. in further contrast to traditional current mode switchers, v c pin ripple is generally not an issue with the lt1424-9. the dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the v c voltage changes during the flyback pulse, but is then held during the subsequent switch on portion of the next cycle. this action naturally holds the v c voltage stable during the current comparator sense action (cur- rent mode switching). pcb layout considerations for maximum efficiency, switch rise and fall times are made as short as practical. to prevent radiation and high frequency resonance problems, proper layout of the com- ponents connected to the ic is essential, especially the power paths (primary and secondary). b field (magnetic) radiation is minimized by keeping output diode, switch pin and output bypass capacitor leads as short as possible. e field radiation is kept low by minimizing the length and area of all traces connected to the switch pin. a ground plane should always be used under the switcher circuitry to prevent interplane coupling. the high speed switching current paths are shown sche- matically in figure 1. minimum lead length in these paths are essential to ensure clean switching and minimal emi. the path containing the input capacitor, transformer pri- mary, output switch, the path containing the transformer secondary, output diode and output capacitor are the only ones containing nanosecond rise and fall times. keep these paths as short as possible. high frequency circulating path v out v in high frequency circulating path isolated load 1424 f01 f figure 1
14 lt1424-9 sn14249 14249fs dimensions in inches (millimeters) unless otherwise noted. package descriptio n u n8 package 8-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n8 1197 0.100 0.010 (2.540 0.254) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.130 0.005 (3.302 0.127) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 0.125 (3.175) min 12 3 4 87 6 5 0.255 0.015* (6.477 0.381) 0.400* (10.160) max 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm)
15 lt1424-9 sn14249 14249fs dimensions in inches (millimeters) unless otherwise noted. package descriptio n u s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 lt1424-9 sn14249 14249fs lt/tp 0599 4k ? printed in usa ? linear technology corporation 1998 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com typical applicatio n u C 9v pcmcia type ii isolated lan supply transformer t1 lpri ratio isolation (l w h) i out efficiency coiltronics ctx02-13483 27 m h 1:1 500vac 14 14 2.2mm 200ma 70% part number description comments lt1105 off-line switching regulator built-in isolated regulation without optoisolator ltc ? 1145/46 isolated digital data transceivers up to 200kbps data rate, ul listed lt1170/71/72 5a/3a/1.25a flyback regulators isolated flyback mode for higher currents lt1370/71 6a/3a flyback regulators uses small magnetics lt1372/77 500khz/1mhz boost/flyback regulators uses ultrasmall magnetics lt1424-5 isolated flyback switching regulator same as lt1424-9 but with 5v output lt1425 isolated flyback switching regulator general purpose with external application resistors related parts 1424 ta01 2 1 3 4 8 7 6 5 v c shdn sync sgnd r1 75 w r2 75 w 1 2 3 mbrs130lt3 t1 1:1 4 0.1 m f lt1424-9 47pf c5 220pf c6 220pf c3 10 m f 25v c4 10 m f 25v 1.8k out com ?v 200ma 1000pf c1 10 m f 25v 5v input com c2 10 m f 25v 0.1 m f 100k r ccomp v in v sw pgnd c1, c2, c3, c4: marcon thcs50e1e106z ceramic capacitor, size 1812. (847) 696-2000 t1: coiltronics ctx02-13483 isolation barrier d1 1n5248 d2 mbr0540t4

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